📄 sta.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
entity sta is
port (
clk:in STD_LOGIC;
dir:out std_logic_vector(2 downto 0);
divide:out STD_LOGIC
);
end sta;
architecture a of sta is
begin
if (clk'event and clk='1') then
divide<=not divide;
if(dir="100") then dir<="000";
else dir<=dir+1;
end if;
end if;
end a;
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