counter.vhd

来自「六十进制计数器.电子万年历是计数器的应用之一.年由月的十二进制计数器进位+1得到」· VHDL 代码 · 共 58 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNTER IS 
PORT
    (CLK,CIN,BCD1WR,BCD10WR:IN STD_LOGIC;
     DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
     CO:OUT STD_LOGIC;
     BCD1OUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
     BCD10OUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
    );
END COUNTER;

ARCHITECTURE A OF COUNTER IS 
SIGNAL BCD1N:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL BCD10N:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
   BCD1OUT<=BCD1N;
   BCD10OUT<=BCD10N;
   PROCESS(CLK,BCD1WR)
      BEGIN
      IF BCD1WR='1' THEN
          BCD1N<=DATAIN;
      ELSIF CLK' EVENT AND CLK='1' THEN
           IF CIN='1' THEN
              IF BCD1N=9 THEN
                 BCD1N<="0000";
              ELSE
                 BCD1N<=BCD1N+1;
              END IF ;
           END IF;
      END IF;
      END PROCESS;
   PROCESS(CLK,BCD10WR)
      BEGIN
      IF BCD10WR='1' THEN
           BCD10N<=DATAIN(2 DOWNTO 0);
      ELSIF CLK'EVENT AND CLK='1' THEN
           IF CIN='1' AND BCD1N=9 THEN
              IF BCD10N=5 THEN
                  BCD10N<="000";
              ELSE
                  BCD10N<=BCD10N+1;
              END IF;
           END IF;
      END IF;
      END PROCESS;
   PROCESS(BCD1N,BCD10N,CIN)
      BEGIN
      IF CIN='1' AND BCD1N=9 AND BCD10N=5 THEN
          CO<='1';
      ELSE
          CO<='0';
      END IF ;
      END PROCESS;
END A ;