代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/171519/9747611
vhd xspfpga.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
www.eeworm.com/read/171518/9747624
vhd regfile.vhd
--****************************************************************************************************
-- Register file for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 23.01.2003
--******
www.eeworm.com/read/171518/9747650
vhd alu.vhd
--****************************************************************************************************
-- ALU for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 16.12.2002
--****************
www.eeworm.com/read/171518/9747662
vhd controllogic.vhd
--****************************************************************************************************
-- Control logic for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 11.02.20
www.eeworm.com/read/171518/9747676
vhd bbusmultiplexer.vhd
--****************************************************************************************************
-- B bus multiplexer for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.1
www.eeworm.com/read/171518/9747694
vhd datamux.vhd
--****************************************************************************************************
-- Data multiplexer for ARM memory sybsistem
-- Designed by Ruslan Lepetenok
-- Modified 07.12
www.eeworm.com/read/170596/9797250
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/415944/11046958
bak findmax.vhd.bak
-- Zhen --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity findmax is
port(clk : in std_logic;
feqin : in std_logic;
datain
www.eeworm.com/read/415944/11047251
vhd findmax.vhd
-- Zhen --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity findmax is
port(clk : in std_logic;
feqin : in std_logic;
datain
www.eeworm.com/read/415874/11049612
vhd uart.vhd
--
-- uart.vhd
--
-- 8-N-1 serial interface
--
-- wr, rd should be one cycle long => trde, rdrf goes 0 one cycle later
--
-- Author: Martin Schoeberl martin@good-ear.com
--
--
-- resources