xspfpga.vhd

the vhdl model of usb. it is very helpful.

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-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--     
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--     
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--     
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--------------------------------------------------------------------------------
-- Project:      Full-Speed USB 1.1 Function Controller
-- File:         xspFPGA.vhd
-- Description:  XSP-010 board, FPGA top level.
-- Version:      FB, 2000jul29
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity xspFPGA is
	port(
		ALE:   in    STD_LOGIC;
		OSC:   in    STD_LOGIC;
		PSEN:  in    STD_LOGIC;
		RD:    in    STD_LOGIC;
		T0:    in    STD_LOGIC;
		TXD:   in    STD_LOGIC;
		WR:    in    STD_LOGIC;
		P2:    in    STD_LOGIC_VECTOR (7 downto 0);
		PC_D:  in    STD_LOGIC_VECTOR (7 downto 0);
		CE:    out   STD_LOGIC;
		OE:    out   STD_LOGIC;
		RST:   out   STD_LOGIC;
		XTAL1: out   STD_LOGIC;
		A:     out   STD_LOGIC_VECTOR (7 downto 0);
		S:     out   STD_LOGIC_VECTOR (6 downto 0);
		P0:    inout STD_LOGIC_VECTOR (7 downto 0);
		P1:    inout STD_LOGIC_VECTOR (7 downto 0)
		);
end xspFPGA;

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architecture BHV of xspFPGA is
	
	---- Signal declarations used on the diagram ----
	
	signal AII : STD_LOGIC_VECTOR (15 downto 0);
	signal BUS530 : STD_LOGIC_VECTOR (7 downto 0);
	signal NET538 : STD_LOGIC;
	
	---- Component declarations -----
	
	component xspCORE
		port (
			A : in STD_LOGIC_VECTOR (15 downto 0);
			DIN : in STD_LOGIC_VECTOR (7 downto 0);
			OSC : in STD_LOGIC;
			PC_D : in STD_LOGIC_VECTOR (7 downto 0);
			RD : in STD_LOGIC;
			WR : in STD_LOGIC;
			DDRV : out STD_LOGIC;
			DOUT : out STD_LOGIC_VECTOR (7 downto 0);
			RST : out STD_LOGIC;
			S : out STD_LOGIC_VECTOR (6 downto 0);
			XTAL : out STD_LOGIC;
			P1 : inout STD_LOGIC_VECTOR (7 downto 0)
			);
	end component;
	component xspUC
		port (
			ALE : in STD_LOGIC;
			DDRV : in STD_LOGIC;
			DOUT : in STD_LOGIC_VECTOR (7 downto 0);
			P2 : in STD_LOGIC_VECTOR (7 downto 0);
			PSEN : in STD_LOGIC;
			RD : in STD_LOGIC;
			A : out STD_LOGIC_VECTOR (15 downto 0);
			CE : out STD_LOGIC;
			OE : out STD_LOGIC;
			P0 : inout STD_LOGIC_VECTOR (7 downto 0)
			);
	end component;
	
begin
	
	----  Component instantiations  ----
	
	Ucore : xspCORE
	port map(
		A => Aii,
		DDRV => NET538,
		DIN => P0,
		DOUT => BUS530,
		OSC => OSC,
		P1 => P1,
		PC_D => PC_D,
		RD => RD,
		RST => RST,
		S => S,
		WR => WR,
		XTAL => XTAL1
		);
	
	Uuc : xspUC
	port map(
		A => Aii,
		ALE => ALE,
		CE => CE,
		DDRV => NET538,
		DOUT => BUS530,
		OE => OE,
		P0 => P0,
		P2 => P2,
		PSEN => PSEN,
		RD => RD
		);
	
	
	---- Terminal assignment ----
	
	-- Output\buffer terminals
	A(0) <= Aii(0);
	A(1) <= Aii(1);
	A(2) <= Aii(2);
	A(3) <= Aii(3);
	A(4) <= Aii(4);
	A(5) <= Aii(5);
	A(6) <= Aii(6);
	A(7) <= Aii(7);
	
	
end BHV;

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-- end of file