findmax.vhd.bak

2008年北京市大学生电子设计竞赛程序源代码[测频率

-- Zhen --

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity findmax is
  port(clk       : in  std_logic;
       feqin     : in  std_logic;
       datain     : in  std_logic_vector(7 downto 0);
       dataout     : out  std_logic_vector(7 downto 0)
             );
end;

architecture behav of findmax is

signal outbuff : std_logic_vector(7 downto 0);

begin
process(clk)
     begin
       if clk 'event and clk ='1' then
         if feqin = '0' then outbuff <= "00000000"; 
         else
           if datain > outbuff then outbuff <= datain; end if; 
         end if;
       end if;                 
end process;


process(feqin)
  begin
    if feqin 'event and feqin ='0' then
    dataout <= outbuff;
    end if;
end process;

end;