代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/392438/8342501

vhd speakera.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity speakera is port(clk:in std_logic; tone:in std_logic_vector(10 downto 0); spks:out std_logic);
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www.eeworm.com/read/392286/8352524

vhd cntm9999.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity cntm9999 is port(dout:out std_logic_vector(6 downto 0); scan: out std_logic_
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www.eeworm.com/read/392284/8352549

vhd nw.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity nw is port(clk: in std_logic; clear: in std_logic;
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www.eeworm.com/read/370579/9595064

txt 米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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www.eeworm.com/read/370579/9595103

txt 带莫尔_米勒输出的状态机.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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www.eeworm.com/read/370579/9595115

txt 莫尔型状态机2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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www.eeworm.com/read/370579/9595131

txt 莫尔型状态机1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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www.eeworm.com/read/370227/9607734

txt 带摩尔 ——米勒输出的状态机.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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www.eeworm.com/read/370226/9607737

txt mealy1 米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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www.eeworm.com/read/173924/9630087

txt 2(1).txt

LIBRARY IEEE; Use IEEE.Std_Logic_1164.ALL; Use IEEE.Std_Logic_Unsigned.All; Entity cnt10 Is Port(clk,rst,EN:In Std_Logic; sdata:In Std_Logic_Vector(3 downto 0); seg:Out Std_Logic_Vect
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