2(1).txt

3-8译码器,BCD码转换10进制,计数器

LIBRARY  IEEE;
Use IEEE.Std_Logic_1164.ALL;
Use IEEE.Std_Logic_Unsigned.All;
Entity cnt10 Is
Port(clk,rst,EN:In Std_Logic;
     sdata:In Std_Logic_Vector(3 downto 0);
     seg:Out Std_Logic_Vector(6 downto 0);
     cout:Out Std_Logic);
End cnt10;

Architecture behav Of cnt10 Is
 signal s:Std_Logic_Vector(3 downto 0);
 Begin 
  Process(clk,rst,sdata)
     variable QI:Std_Logic_Vector(3 downto 0);
      Begin
        If rst='1' Then 
           QI:=(Others=>'0');
        Elsif clk'event and clk='1' Then 
          If EN='1' THEN
          QI:=sdata; 
          elsif EN='0' then
           If QI<9 Then 
             QI:=QI+1;
           Else QI:=(Others=>'0');
           End If;
          End IF;
        End If;
     If QI=9 Then
        cout<='1';
     Else
        cout<='0';
     End If;
    case QI is
	  When "0000"=>seg<="0111111";
      When "0001"=>seg<="0000110";
      When "0010"=>seg<="1011011";
      When "0011"=>seg<="1001111";
      When "0100"=>seg<="1100110";
      When "0101"=>seg<="1101101";
      When "0110"=>seg<="1111101";
      When "0111"=>seg<="0000111";
      When "1000"=>seg<="1111111";
      When "1001"=>seg<="1101111";
      When Others=>NULL;
	end case;

End Process;
  
End behav;