📄 cntm9999.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cntm9999 is
port(dout:out std_logic_vector(6 downto 0);
scan: out std_logic_vector(1 downto 0);
clk:in std_logic;
load:in std_logic;
en: in std_logic;
updn: in std_logic;
co:out std_logic;
d1:in std_logic_vector(3 downto 0);
d2:in std_logic_vector(3 downto 0);
d3:in std_logic_vector(3 downto 0);
d4:in std_logic_vector(3 downto 0));
end;
architecture art of cntm9999 is
signal co1: std_logic;
signal co2: std_logic;
signal co3: std_logic;
signal data:std_logic_vector(3 downto 0);
signal cnt4:std_logic_vector(1 downto 0);
signal q1:std_logic_vector(3 downto 0);
signal q2:std_logic_vector(3 downto 0);
signal q3:std_logic_vector(3 downto 0);
signal q4:std_logic_vector(3 downto 0);
signal CLK10_1 : std_logic;
begin
------------------------------------------20分频
PROCESS(CLK)
VARIABLE COUNT:INTEGER RANGE 0 TO 9;
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF COUNT=9 THEN
CLK10_1<=NOT CLK10_1;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
END IF;
END PROCESS;
------------------9999进制加减计数器
------------------个位
process(CLK10_1,load)
begin
if load='1' then q1<=d1;
elsif rising_edge(CLK10_1) then
if en='1' then
if updn='1' then
if q1="1001" then
q1<="0000";co1<='1';
else
q1<=q1+1;co1<='0';
end if;
elsif updn='0' then
if q1="0000" then
q1<="1001";co1<='1';
else
q1<=q1-1;co1<='0';
end if;
end if;
end if;
end if;
end process;
------------------十位
PROCESS(co1,load)
BEGIN
IF load='1' THEN
Q2<=D2;
ELSIF (CO1'EVENT AND CO1='1') THEN
if en='1' then
IF UPDN='1' THEN
IF Q2="1001" THEN
Q2<="0000";CO2<='1';
ELSE
Q2<=Q2+1;CO2<='0';
END IF;
ELSIF UPDN='0' THEN
IF Q2="0000" THEN
Q2<="1001";CO2<='1';
ELSE
Q2<=Q2-1;CO2<='0';
END IF;
END IF;
end if;
END IF;
END PROCESS;
------------------百位
process(co2,load)
begin
if load='1' then q3<=d3;
elsif rising_edge(co2) then
if en='1' then
if updn='1' then
if q3="1001" then
q3<="0000";co3<='1';
else
q3<=q3+1;co3<='0';
end if;
elsif updn='0' then
if q3="0000" then
q3<="1001";co3<='1';
else
q3<=q3-1;co3<='0';
end if;
end if;
end if;
end if;
end process;
------------------
process(co3,load)
begin
if load='1' then q4<=d4;
elsif rising_edge(co3) then
if en='1' then
if updn='1' then
if q4="1001" then
q4<="0000";co<='1';
else
q4<=q4+1;co<='0';
end if;
elsif updn='0' then
if q4="0000" then
q4<="1001";co<='1';
else
q4<=q4-1;co<='0';
end if;
end if;
end if;
end if;
end process;
------------------4进制计数器
process(clk)
begin
if (clk'event and clk='1') then
if (cnt4="11") then
cnt4<="00";
else
cnt4<=cnt4+'1';
end if;
end if;
end process;
------------------数码管地址扫描
process(cnt4)
begin
case cnt4 is
when "00"=>scan<="00";data<=q1;
when "01"=>scan<="01";data<=q2;
when "10"=>scan<="10";data<=q3;
when "11"=>scan<="11";data<=q4;
when others=>null;
end case;
end process;
------------------8段译码
process(data)
begin
case data is
when "0000"=>dout<="0111111"; ----显示0
when "0001"=>dout<="0000110"; ----显示1
when "0010"=>dout<="1011011"; ----显示2
when "0011"=>dout<="1001111"; ----显示3
when "0100"=>dout<="1100110"; ----显示4
when "0101"=>dout<="1101101"; ----显示5
when "0110"=>dout<="1111101"; ----显示6
when "0111"=>dout<="0000111"; ----显示7
when "1000"=>dout<="1111111"; ----显示8
when "1001"=>dout<="1101111"; ----显示9
when others=>null;
end case;
end process;
end;
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