代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/211745/15174516
vhd counter100.vhd
--counter100
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter100 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/211745/15174531
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/211745/15174538
vhd counter100.vhd
--counter100
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter100 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/211745/15174576
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/211745/15174701
vhd counter_1024.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1024 is
port(clk,clr,en,updn,bcdwr:in std_logic;
datain:in std_logic_vector(9 downt
www.eeworm.com/read/211218/15184637
vhd cal_ctl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
entity cal_ctl is
p
www.eeworm.com/read/210918/15189905
vhd pll.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pll is
port(clk_in,data_in : in std_logic;
clk_out,state,data_ou
www.eeworm.com/read/209602/15216772
vhd fen24.vhd
-------------------------------------------------
--实体名：fen24
--功 能：24进制计数器
--接 口：clk -时钟输入
-- qout1-个位BCD输出
-- qout2-十位BCD输出
-- carry-进位信号输出
-----------------------
www.eeworm.com/read/206760/15290188
vhd cdu99.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cdu99 is
port (
clk,reset:in std_logic;
count11:out std_logic_vec
www.eeworm.com/read/168634/5441302
vhd alub.vhd
-- ************************************************************************
-- * NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE *
-- *