代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/255018/12106026
vhd cnt10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT (CLK,RST,EN : IN STD_LOGIC;
CQ : OUT STD_LOGIC_VECTO
www.eeworm.com/read/341091/12109057
vhd alu.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ALU IS
PORT(
AC, DR: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S1, S0: IN S
www.eeworm.com/read/152451/12112451
vhd vga.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
www.eeworm.com/read/152166/12135094
vhdl signal1.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity signal1 is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end signal1;
archite
www.eeworm.com/read/340484/12154127
vhd br_gen.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity br_gen is
generic(divisor: integer := 26);
port(
sysclk:in std_logic;
sel :in std_
www.eeworm.com/read/340475/12155498
vhd lock.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity lock is
port(
clk:in std_logic;
keyin:in std_logic_vector(7 downto 0);
lockon: in std_logic;
www.eeworm.com/read/253980/12171155
vhd xspfpga.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
www.eeworm.com/read/151714/12179477
vhd t80_reg.vhd
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source
www.eeworm.com/read/339666/12210962
vhd mul3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mul3 is
port(in1,in2,in3:std_logic_vector(7 downto 0);
sela,selb,selc:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
e
www.eeworm.com/read/339666/12211072
vhd txmit.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmit is
port(
tx:out std_logic;
--data:in std_logic_vector(7 downto 0);
mclk_16,write:in std_logic