代码搜索:Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
www.eeworm.com/read/346137/11766476

vhd zhongbai.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity zhongbai is port(clk:in std_logic; rst:in std_logic; q:out std_logic_vector(7 downto 0)); end; architecture
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vhd counter24.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter24 is Port ( clk : in std_logic; reset : in std_logic; din : in std_logic_vector(7
www.eeworm.com/read/345690/11795168

txt 莫爾形狀態機2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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txt 帶莫爾_米勒輸出的狀態機.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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txt 莫爾形狀態機1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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txt 米勒形狀態機.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
www.eeworm.com/read/156108/11826991

vhd cnta.vhd

LIBRARY IEEE; -- 24进制计数器 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNTA IS PORT ( CLK : IN STD_LOGIC; U_D : IN STD_LO
www.eeworm.com/read/155883/11840649

vhd count_0_9.vhd

--******************************** --* Counter From 0 To 9 * --* Filename : COUNT_0_9.VHD * --******************************** library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.
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vhd count_0_5.vhd

--******************************** --* Counter From 0 To 5 * --* Filename : COUNT_0_5.VHD * --******************************** library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.
www.eeworm.com/read/155467/11869581

vhd cnt10.vhd

--Author : 屈峥 2002081212 --File Name : cnt10.vhd --Objective : 10进制计数器 -- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT (CLK,RST,EN