counter24.vhd

来自「基于FPGA的多功能电子时钟的设计很经典的哦」· VHDL 代码 · 共 37 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter24 is
    Port ( clk : in std_logic;
         reset : in std_logic;
         din : in std_logic_vector(7 downto 0);
         dout : out std_logic_vector(7 downto 0);
         c:out std_logic);
end counter24;
architecture Behavioral of counter24 is
signal count : std_logic_vector(7 downto 0);
begin
	process(clk,reset)
	begin
	   if reset= '0' then
		   count <= din;
		   c<='0';
       elsif rising_edge(clk) then	   
		   if count(3 downto 0)="1001" then
			 count(3 downto 0)<="0000";
			count(5 downto 4)<=count(5 downto 4) +1;
			c<='0';
         else
			count(3 downto 0)<=count(3 downto 0)+1;
			c<='0';
         end if;
		 if count="00100011" then
		   count<="00000000";
		   c<='1';
         end if;
      end if;
    dout <= count;
   end process;
end Behavioral;