count_0_5.vhd

来自「設計VHDL24小時的時鐘」· VHDL 代码 · 共 43 行

--********************************
--*     Counter From 0 To 5      *
--*   Filename : COUNT_0_5.VHD   *
--********************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity COUNT_0_5 is
    Port ( CLK   : in std_logic;
           RESET : in std_logic;
		 CE    : in std_logic;
		 CARRY : out std_logic;
		 BCD	  : out std_logic_vector(3 downto 0));
end COUNT_0_5;

architecture Behavioral of COUNT_0_5 is
  signal FIVE    : std_logic;
  signal COUNTER : std_logic_vector(3 downto 0);
begin
  process (CLK,RESET)

   begin
	if RESET    = '0' then 
	   COUNTER <= "0000";
	elsif CLK'event and CLK = '1' then
	  if CE     = '1' then
	     if COUNTER  = "0101" then
	        COUNTER <= "0000";
	     else
	        COUNTER <= COUNTER + 1;
		end if;
	  end if;
	end if;
  end process;
  FIVE  <= '1' when COUNTER = "0101" else '0';
  CARRY <=  FIVE and CE; 
  BCD   <= COUNTER;

end Behavioral;