代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/402992/11525061
vhd ch4_5_4.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--*********************************************************
-- 4 BITS SUBSTRACTOR OPERA
www.eeworm.com/read/402992/11525402
vhd keyboard1.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY KEYBOARD1 IS
PORT (
clk
www.eeworm.com/read/402550/11533377
txt tlc5510_vhdl.txt
--文件名：TLC5510.vhd
--功能：基于VHDL语言，实现对高速A/D器件TLC5510控制
--最后修改日期：2004.3.20
library ieee;
use ieee.std_logic_1164.all;
entity tlc5510 is
port(clk :in std_logic; --系统时钟
www.eeworm.com/read/402018/11543790
vhd txmit.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmit is
port(
tx:out std_logic;
--data:in std_logic_vector(7 downto 0);
mclk_16,write:in std_logic
www.eeworm.com/read/402018/11543791
vhd rxcver.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity RXCVER is
--generic:constant:std_logic;
port
www.eeworm.com/read/402018/11543813
vhd mul3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mul3 is
port(in1,in2,in3:std_logic_vector(7 downto 0);
sela,selb,selc:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
e
www.eeworm.com/read/402018/11543827
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/402018/11543885
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/402018/11543892
vhd counter100.vhd
--counter100
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter100 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/402018/11543907
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;