ch4_5_4.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 38 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

--*********************************************************
-- 4 BITS SUBSTRACTOR OPERATOR
--*********************************************************
--
entity CH4_5_4 is
     port
     (    A : in UNSIGNED (3 downto 0);
          B : in UNSIGNED (3 downto 0);
		  Cin : in STD_LOGIC ;
          BCDout :  out STD_LOGIC_VECTOR (3 downto 0) ;
          Cout : out STD_LOGIC 
           );
end CH4_5_4;
--*********************************************************
architecture A of CH4_5_4 is
      SIGNAL C,Y : STD_LOGIC_VECTOR (3 downto 0) ;
begin

	Y(0) <= A(0) XOR B(0) XOR Cin ;

     C(0) <= (Cin AND NOT A(0))  OR (Cin AND B(0)) OR (NOT A(0) AND B(0));

GEN: FOR I IN 1 TO 3 GENERATE
     Y(I) <= A(I) XOR B(I) XOR C(I-1);
     C(I) <= (C(I-1) AND NOT A(I))  OR (C(I-1) AND B(I)) OR (NOT A(I) AND B(I));
     END GENERATE;
Cout <= C(3) ;

BCDout <=  Y(3) & Y(2) & Y(1) & Y(0) ;

end A;
--*********************************************************