keyboard1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;

LIBRARY altera;
USE altera.maxplus2.ALL;


ENTITY KEYBOARD1 IS
	PORT (  
			clk : IN STD_LOGIC ;  --system original clock
--	        Q_OUT     : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);    --count result of "clk"
--			CNT_OUT  : OUT STD_LOGIC_VECTOR (1 downto 0);     --***
--			CNTA: OUT STD_LOGIC_VECTOR (3 downto 0) ;  --XX
--			CNTB: OUT STD_LOGIC;      --XX
			clk_scan : OUT STD_LOGIC_VECTOR (3 downto 0) ;  --scan sequence
			key_in: IN STD_LOGIC_VECTOR (3 downto 0) ; --KEY IN button code
            out_numb : OUT STD_LOGIC_VECTOR(3 downto 0) ;
			out_func :  OUT STD_LOGIC_VECTOR(6 downto 0) ;
			flag_numb : OUT STD_LOGIC ;
			flag_Func : OUT STD_LOGIC 			); 
END KEYBOARD1 ;

ARCHITECTURE a OF KEYBOARD1 IS 

	component debouncing
		port(  d_in   : IN STD_LOGIC ;
			   clk    : IN STD_LOGIC ;	
			   d_out  : OUT STD_LOGIC ) ;
	end component ;
	SIGNAL CNT: STD_LOGIC_VECTOR(1 downto 0) ;  --*** "B"
--	SIGNAL A: STD_LOGIC_VECTOR(3 downto 0) ;
	SIGNAL C: STD_LOGIC_VECTOR(3 downto 0) ;
--	signal CLKB : std_logic ; 
BEGIN
--*******************************************
-- scan signal generator 
counter : block
	Signal  Q    : STD_LOGIC_VECTOR(19 DOWNTO 0);           	
-- 	Signal 	CNT, S : STD_LOGIC_VECTOR(1 DOWNTO 0);  --keyboard scan about 15Hz ***
 	Signal 	S : STD_LOGIC_VECTOR(1 DOWNTO 0);  --keyboard scan about 15Hz ***

	SIGNAL 	SEL   : STD_LOGIC_VECTOR (3 downto 0);

BEGIN

	PROCESS (Clk)				       
	Begin
		IF CLK'Event AND CLK='1' then
			Q <= Q+1;
--			CNT <= Q(18 DOWNTO 17) ;	-- about 15Hz  61/4=15	
			CNT <= Q(4 DOWNTO 3) ;	    -- ***
		END IF;
	END PROCESS;
									     
			SEL <= 	"1110" WHEN S=0 ELSE
					"1101" WHEN S=1 ELSE
					"1011" WHEN S=2 ELSE
					"0111" WHEN S=3 ELSE
					"1111";

	S <= CNT ;        -- *** 
--	CNT_OUT <= CNT ;  -- *** 
--	Q_OUT <= Q ;   
	CLK_SCAN <= SEL ;

end block counter ;
--
--*********************************************
--
--debounuing ckt
debounuing : block
--	SIGNAL A: STD_LOGIC_VECTOR(3 downto 0) ;
begin
	U1: debouncing PORT MAP (
					d_in => key_in(0) ,
					d_out => C(0) ,
					clk => clk 
					);
	U2: debouncing PORT MAP (
					d_in => key_in(1) ,
					d_out => C(1)  ,
					clk => clk
					 );
	U3: debouncing PORT MAP (
					d_in => key_in(2) ,
					d_out => C(2)  ,
	     			clk => clk 
					);
	U4: debouncing PORT MAP (
	     			d_in => key_in(3) ,
					d_out => C(3)  ,
					clk => clk 
					);
END block debounuing  ;
--
--******************************************************
--key_decoder

key_decoder : block 
signal ff : std_logic ;
signal Z : std_logic_VECTOR(5 downto 0) ;
signal T : std_logic_VECTOR(6 downto 0) ;
signal F : std_logic_VECTOR(3 downto 0); 
begin

PROCESS(clk)
begin
	FF <= (not key_in(3) and key_in(2) and key_in(1) and key_in(0) ) or 
          (key_in(3) and not key_in(2) and key_in(1) and key_in(0) ) or   
          (key_in(3) and key_in(2) and not key_in(1) and key_in(0) ) or 
          (key_in(3) and key_in(2) and key_in(1) and not key_in(0) ) ;
--	Z <= clk_cntb & key_in ;
	Z <= CNT & C ;
IF CLK'EVENT  AND CLK = '1'  THEN
		case Z is
					when "000111" => F <= "0000" ; --0
					when "001011" => F <= "0001" ; --1
					when "001101" => F <= "0010" ; --2
					when "001110" => F <= "0011" ; --3
					when "010111" => F <= "0100" ; --4
					when "011011" => F <= "0101" ; --5
					when "011101" => F <= "0110" ; --6
					when "011110" => F <= "0111" ; --7
					when "100111" => F <= "1000" ; --8
					when "101011" => F <= "1001" ; --9
					when others   => F <= "1111" ;
		end case ;
END IF ;
out_numb <= F ;

IF CLK'EVENT  AND CLK = '1'  THEN
		case  Z is
					when "101101" => T <= "0000010" ;--A_BACK
					when "101110" => T <= "0000100" ;--B_CLEAR
					when "110111" => T <= "0001000" ;--C_CODE_RESET
					when "111011" => T <= "0010000" ;--D_CODE_RENEW
					when "111101" => T <= "0100000" ;--E_LOCK
					when "111110" => T <= "1000000" ;--F_CHECK_CODE
					when others  =>  T <= "0000001" ;
				end case ;					
END IF ;
end process ;
flag_numb <=    (NOT F(3) AND NOT F(2) AND NOT F(1) AND NOT F(0) ) OR  --0
			    (NOT F(3) AND NOT F(2) AND NOT F(1) AND F(0) ) OR  --1
			    (NOT F(3) AND NOT F(2) AND F(1) AND NOT F(0) ) OR
			    (NOT F(3) AND NOT F(2) AND F(1) AND F(0) ) OR
			    (NOT F(3) AND F(2) AND NOT F(1) AND NOT F(0) ) OR
			    (NOT F(3) AND F(2) AND NOT F(1) AND F(0) ) OR
			    (NOT F(3) AND F(2) AND F(1) AND NOT F(0) ) OR
			    (NOT F(3) AND F(2) AND F(1) AND F(0) ) OR
			    (F(3) AND NOT F(2) AND NOT F(1) AND NOT F(0) ) OR
			    (F(3) AND NOT F(2) AND NOT F(1) AND F(0) ) ;
flag_func <= T(6) OR T(5) OR T(4) OR T(3) OR T(2) OR T(1)  ;
out_func <= T ;


end block key_decoder ;

--=========================================================






END a;