代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
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vhd uart.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is
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vhd wprot.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is
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vhd mctrl.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is
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vhd leonlib.vhd
-----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This program is
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vhd vga_display.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity vga_display is
port
(
clk: in std_logic; -- 25.2MHz
ena: in std_logic; -- from vga_ctrl
data: in st
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vhd service_module.vhd
--**********************************************************************************************
-- Some additional control registers for the AVR Core
-- Version 0.7 20.05.2003
-- Designed by Rusla
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vhd io_reg_file.vhd
--************************************************************************************************
-- Internal I/O registers (implemented inside the core) decoder/multiplexer
-- for AVR core
-- Versi
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vhd rsacypher.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
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vhd ch4_1_2_1.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY CH4_1_2 IS
PORT (A : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
EN : IN STD_LOGIC ;
Y : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0))
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vhd ch4_5_2.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--*********************************************************
-- check 4-BIT adder funct