ch4_1_2_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;

ENTITY  CH4_1_2  IS
  PORT (A : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
        EN       : IN STD_LOGIC ;
        Y  : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0)) ;
END CH4_1_2 ;

ARCHITECTURE  ENDEC OF CH4_1_2 IS

BEGIN
    Y(2) <= (A(7) OR A(6) OR A(5) OR A(4)) AND EN ;
	Y(1) <= (A(7) OR A(6) OR A(3) OR A(2) ) AND EN ;
	Y(0) <= (A(7) OR A(5) OR A(3) OR A(1) ) AND EN ;
  END ENDEC ;