ch4_5_2.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

--*********************************************************
-- check 4-BIT  adder function
--*********************************************************
--
entity CH4_5_2 is
     port
     (    A : in UNSIGNED (3 downto 0);
          B : in UNSIGNED (3 downto 0);
		  Cin : in STD_LOGIC ;
          BCDout :  out STD_LOGIC_VECTOR (3 downto 0) ;
          Cout : out STD_LOGIC 
           );
end CH4_5_2 ;
--*********************************************************
architecture ARCH of CH4_5_2 is

      SIGNAL Y,C: STD_LOGIC_VECTOR (3 downto 0) ;
begin
		Y(0) <= A(0) XOR B(0) XOR Cin ;
		Y(1) <= A(1) XOR B(1) XOR C(0) ;
		Y(2) <= A(2) XOR B(2) XOR C(1) ;
		Y(3) <= A(3) XOR B(3) XOR C(2) ;
		C(0) <= (Cin AND A(0))  OR (Cin AND B(0)) OR (A(0) AND B(0));
		C(1) <= (C(0) AND A(1))  OR (C(0) AND B(1)) OR (A(1) AND B(1));
		C(2) <= (C(1) AND A(2))  OR (C(1) AND B(2)) OR (A(2) AND B(2));
		C(3) <= (C(2) AND A(3))  OR (C(2) AND B(3)) OR (A(3) AND B(3));
	BCDout <= Y(3) & Y(2) & Y(1) & Y(0) ;
	Cout <= C(3) ;
end ARCH ;
--*********************************************************