代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/408876/11366814
vhd lcd_wave.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY LCD_WAVE IS
PORT(CLK:IN STD_LOGIC;
REQ:OUT STD_LOGIC;
BUSY:IN STD_LOGIC
www.eeworm.com/read/408876/11366859
vhd count60.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY COUNT60 IS
PORT(CLK:IN STD_LOGIC;
CO:OUT STD_LOGIC;
EN:IN STD_LOGIC;
www.eeworm.com/read/263314/11367742
txt mealy1.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/263314/11367746
txt state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/263314/11367830
txt moor1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/263314/11367847
txt moor2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/262752/11391901
vhd cnt6.vhd
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY cnt6 IS
PORT(
clk,clr,en : IN STD_LOGIC;
q : buffer STD_LOGIC_VECTOR(2 downto 0);
c6
www.eeworm.com/read/408027/11406389
txt 出租车计价器vhdl程序.txt
--文件名：taxi.hd。
--功能：出租车计价器。
--最后修改日期：2008.4.9。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity taxi is
port ( clk_240 :in std
www.eeworm.com/read/407961/11406995
vhd dncnten.vhd
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_log
www.eeworm.com/read/407665/11412337
vhd dcache.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is