cnt6.vhd

来自「数字秒表的整个设计以及程序．波形仿真都在里面的了」· VHDL 代码 · 共 35 行

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY cnt6 IS
PORT(
		clk,clr,en	: IN	STD_LOGIC;
		q	        : buffer	STD_LOGIC_VECTOR(2 downto 0);
	    c6	        : OUT	STD_LOGIC
    );
END cnt6;

ARCHITECTURE one OF cnt6 IS
BEGIN
process(clr,clk)
begin
   if clr='1' then q<="000";
   elsif clk'event and clk='1' then
        if en='1' then 
            if(q<5) then q<=q+1;
            else q<="000";
            end if;
        end if;
   end if;
end process;

process(q)
begin
  if q="101" then c6<='1';
     else c6<='0';
  end if;
end process;
END one;