📄 count60.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY COUNT60 IS
PORT(CLK:IN STD_LOGIC;
CO:OUT STD_LOGIC;
EN:IN STD_LOGIC;
DOUT:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END ENTITY;
ARCHITECTURE ART OF COUNT60 IS
SIGNAL CNT:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF EN='1' THEN
IF CNT="111011" THEN
CNT<="000000";CO<='1';
ELSE
CNT<=CNT+1;CO<='0';
END IF;
END IF;
END IF;
END PROCESS;
DOUT<=CNT;
END ARCHITECTURE;
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