代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/476967/6743611

vhd minute.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity minute is port(reset,clk,sethour:in std_logic; enhour:out std_logic;--进位 daout:out std_logic_vector(7 downto
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www.eeworm.com/read/410626/11274379

vhd square.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY square IS PORT(clk0,fq:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END; ARCHITECTURE behave OF
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www.eeworm.com/read/410626/11274382

vhd ladder.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ladder IS PORT(clk0,fq:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ladder; ARCHITECTURE behave
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www.eeworm.com/read/410626/11274387

bak square.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY square IS PORT(clk0,fq:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END; ARCHITECTURE behave OF
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www.eeworm.com/read/410626/11274406

bak delta.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY delta IS PORT(clk0,fq:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); end delta; ARCHITEC
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www.eeworm.com/read/410626/11274565

bak ladder.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ladder IS PORT(clk0,fq:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ladder; ARCHITECTURE behave
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www.eeworm.com/read/410626/11274569

vhd delta.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY delta IS PORT(clk0,fq:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); end delta; ARCHITEC
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www.eeworm.com/read/410563/11277001

vhd cnt6.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt6 is port(clk :in std_logic; ena :in std_logic; clr :in std_logic;
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www.eeworm.com/read/410563/11277053

vhd cnt10.vhd

library ieee; --十进制 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt10 is port(clk :in std_logic; ena :in std_logic; clr :in std_l
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www.eeworm.com/read/410210/11298219

txt 步进电机及伺服电机的控制.txt

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for ins
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