📄 delta.vhd.bak
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY delta IS
PORT(clk0,fq:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end delta;
ARCHITECTURE behave OF delta IS
signal i:integer range 0 to 20;
signal clk2:std_logic;
BEGIN
process(fq,clk0)
begin
if fq'event and fq='1' then
if i<20 then i<=i+2;
else i<=0;
end if;
end if;
END PROCESS;
process(i,clk0)
variable tem:integer range 0 to 22;
variable qq:std_logic;
begin
if clk0'event and clk0='1' then
if tem<i then tem:=tem+1;
else tem:=0;qq:=not qq;
end if;
end if;
clk2<=qq;
end process;
PROCESS(clk2)
VARIABLE tmp:STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE a:STD_LOGIC;
BEGIN
IF clk2'EVENT AND clk2='1' THEN
IF a='0' THEN
IF tmp="11111110" THEN
tmp:="11111111";
a:='1';
ELSE
tmp:=tmp+1;
END IF;
ELSE
IF tmp ="00000001" THEN
tmp:="00000000";
a:='0';
ELSE
tmp:=tmp-1;
END IF;
END IF;
END IF;
q<=tmp;
END PROCESS;
END behave;
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