eda.vhd

来自「能够产生方波、三角波、正弦波、及阶梯波」· VHDL 代码 · 共 40 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY EDA IS 
 PORT(    funset:in std_logic;
      fqset,clk:in std_logic;
            update:out std_logic_vector(7 downto 0));
END ENTITY EDA;
ARCHITECTURE behave OF EDA IS
	
    COMPONENT sin
		PORT(clk0,fq:in std_logic;
		           q:out std_logic_vector(7 downto 0));
    END COMPONENT sin;
    COMPONENT delta
        PORT(clk0,fq:in std_logic;
		           q:out std_logic_vector(7 downto 0));
    END COMPONENT delta;
    COMPONENT square
  		PORT(clk0,fq:in std_logic;
		           q:out std_logic_vector(7 downto 0));
    END COMPONENT square;
    COMPONENT ladder
		PORT(clk0,fq:in std_logic;
		           q:out std_logic_vector(7 downto 0));
    END COMPONENT ladder;
    COMPONENT setfun
  		PORT(In1,In2,In3,In4:in std_logic_vector(7 downto 0);
			      set:in std_logic;
				 	q:out std_logic_vector(7 downto 0));
	END COMPONENT setfun;
	SIGNAL q1,q2,q3,q4:std_logic_vector(7 downto 0);
	
  BEGIN
	
	u1:sin PORT MAP(clk0=>clk,q=>q1,fq=>fqset);
	u2:delta PORT MAP(clk0=>clk,q=>q2,fq=>fqset);
	u3:square PORT MAP(clk0=>clk,q=>q3,fq=>fqset);
	u4:ladder PORT MAP(clk0=>clk,q=>q4,fq=>fqset);
	u5:setfun PORT MAP(set=>funset,In1=>q4,In2=>q1,In3=>q2,In4=>q3,q=>update);
  END behave;