步进电机及伺服电机的控制.txt

本程序采用vhdl语言对步进电机及伺服电机进行控制

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ztsd is
    Port (clk,key,rst:in std_logic;  --系统时时钟/换向按键/复位信号
    	y:out std_logic ;        --输出
		sel:out std_logic);
end ztsd;

architecture Behavioral of ztsd is
signal sel1:std_logic;
begin

process(key,clk,rst)    --产生换向延时秒脉冲
variable cnt:integer range 0 to 32000000;
begin
	if rst='0' then cnt:=0;
	elsif key='1' then cnt:=0;
	else if rising_edge(clk) then 
			if cnt<32000000 then cnt:=cnt+1;y<='0';
			else cnt:=32000000;y<='1';
			end if;
		end if;
	end if;	
end process;

process(key,sel1,rst)
begin
	if rst='0' then sel1<='1';
	elsif rising_edge(key) then 
	sel1<=not sel1;
	end if;
sel<=sel1;
	end process;

end Behavioral;

--/*STEP_MOTOR.VHD*/--步进电机控制脉冲产生模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity step_motor is
    Port ( clk,rst : in std_logic;  --系统时钟/复位信号
	     sel : in std_logic;     --正反转切换键
		 clkkk:out std_logic;   --步进电机步进脉冲
		 control:out std_logic_vector(3 downto 0)); --步机电机四相输出
end step_motor;
architecture Behavioral of step_motor is
signal clkk:std_logic;
type step is array (0 to 7) of std_logic_vector(3 downto 0);
constant eight_step:step:=("0001", "0011","0010","0110","0100","1100","1000","1001");
begin

process(clk,rst)  --电机运转脉冲分频模块
variable cnt:integer range 0 to 1499999;
begin
	if rst='0' then cnt:=0;
	elsif clk'event and clk='1' then 
		if cnt>=7	then clkk<=not clkk;cnt:=0;
		else cnt:=cnt+1;
		end if;
		end if;
end process;
clkkk<=clkk;

process(clkk,sel,rst)  --控制脉冲产生模块
variable index:integer range 0 to 7:=0;
begin			
	if rst='0' then index:=0;				
    elsif rising_edge(clkk) then
    		if sel='1' then
		if index<=6 then  
		index:=index+1;
		else index:=0;
		end if;
		else if index>=1 then 
		index:=index-1;
		else index:=7;
		end if;
		end if;
		control<=eight_step(index);
		end if;
end process;

end Behavioral; 

--/*CEPIN.VHD*/--测频模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cepin is
    Port (clk,clk1,rst:in std_logic; --系统时钟/输入被测脉冲/复位信号
	 	 shift:out std_logic_vector(3 downto 0); --数码管位选信号
		 data_led:out std_logic_vector(7 downto 0) ); --七段数码管
end cepin;

architecture Behavioral of cepin is
signal count,d2:std_logic_vector(15 downto 0):=(others=>'0');
signal clkkk:std_logic;
signal clkk:std_logic:='0';
signal data_ledin:std_logic_vector(3 downto 0);

begin

cepin:block --测频模块
begin
process(clk,rst)
variable cnt:integer range 1 to 32000000;
begin
	if rst='0' then cnt:=1;
	elsif rising_edge(clk) then 
		if cnt>=32000000 then 
			clkk<=not clkk;
			cnt:=1;
		else
			cnt:=cnt+1;
		end if;
	end if;
end process;

process(clkk,clk1,rst) 
variable cnt:std_logic_vector(15 downto 0):=(others=>'0');
variable cnt1:integer range 0 to 399;
begin
	if rst='0' then cnt:=(others=>'0');cnt1:=0;
	elsif rising_edge(clk1)  then
	if clkk='1' then
		if cnt1<399 then cnt1:=cnt1+1;
		else cnt1:=0; 
			if cnt(3 downto 0)<9 then
				cnt(3 downto 0):=cnt(3 downto 0)+1;
				else cnt(3 downto 0):="0000";
					if cnt(7 downto 4)<9 then 
					cnt(7 downto 4):=cnt(7 downto 4)+1;
					else cnt(7 downto 4):="0000";
						if cnt(11 downto 8)<9 then 
						cnt(11 downto 8):=cnt(11 downto 8)+1;
						else cnt(11 downto 8):="0000";
							if cnt(15 downto 12)<9 then 
							cnt(15 downto 12):=cnt(15 downto 12)+1;
							else cnt(15 downto 12):="0000";
							end if;
						end if;
					end if;
				end if;
			 end if;
		  else  cnt:=(others=>'0') ;
		end if;					
	end if;
count<=cnt;
end process;
end block;

process(clkk)
begin
if clkk'event and clkk='0' then 
d2<=count;
end if;
end process;

process(clk,rst)
variable cnt:integer range 0 to 79999:=0;
begin
	if rst='0' then cnt:=0;
	elsif rising_edge(clk) then 
	if cnt=79999 then clkkk<=not clkkk;cnt:=0;
	else cnt:=cnt+1;
	end if;
	end if;
end process;

disp:block  --转速显示模块
begin
	process(clkkk,d2,rst)
	variable cnt:std_logic_vector(1 downto 0):="00";
	begin
		if rst='0' then cnt:="00";shift<="1111";data_ledin<="1111";
			elsif rising_edge(clkkk)	    then 
				case cnt is
					when "00"=>shift<="1110";
							 data_ledin<=d2(3 downto 0);
							 cnt:=cnt+1;
					when "01"=>shift<="1101";
							 data_ledin<=d2(7 downto 4);
							 cnt:=cnt+1;
					when "10"=>shift<="1011";
							 data_ledin<=d2(11 downto 8);
							 cnt:=cnt+1;
					when "11"=>shift<="0111";
							 data_ledin<=d2(15 downto 12);
							 cnt:="00";
					when others=>shift<="1111";cnt:="00";
				end case;
			end if;
	end process;
end block;

yima:block
begin
process (data_ledin)               --译码
  begin
     case data_ledin is
         when"0000"=>data_led<="11000000";--0
	      when"0001"=>data_led<="11111001";--1
			when"0010"=>data_led<="10100100";--2
			when"0011"=>data_led<="10110000";--3
			when"0100"=>data_led<="10011001";--4
			when"0101"=>data_led<="10010010";--5
			when"0110"=>data_led<="10000010";--6
			when"0111"=>data_led<="11111000";--7
			when"1000"=>data_led<="10000000";--8
			when"1001"=>data_led<="10010000";--9
			when others=>data_led<="11111111";--No signal; 
       end case;
end process;
end block;

end Behavioral;


--/*BIANPIN.VHD*/--变频模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bianpin is
    Port (rst,clk,sub,add:in std_logic; --复位信号/系统时钟/减速输入/加速输入
    	count:out std_logic );      --已变频率输出
end bianpin;

architecture Behavioral of bianpin is
signal con:integer range 1 to 100:=50;
signal clkk:std_logic:='0';
signal cnt1:integer range 0 to 1100;
begin

process(clkk,add,sub,rst)  --加减键处理模块
variable con1:integer range 1 to 100:=50;
begin
	if rst='0' then con1:=1;
	elsif clkk'event and clkk='1' then 
		if add='0' then 
		if con1<=99 then 
		con1:=con1+1;
		end if;
		elsif sub='0' then 
		if con1>=2 then 
		con1:=con1-1;
		end if;
		end if;
		end if;
con<=con1;
end process;

process(clk,rst) --产生按键检测频率
variable cnt:integer range 0 to 1499999;
begin
	if rst='0' then cnt:=0;
	elsif clk'event and clk='1' then 
		if cnt>=1499999	then clkk<=not clkk;cnt:=0;
		else cnt:=cnt+1;
		end if;
		end if;
end process;

process(clk,con,cnt1,rst) --变频模块
begin
	if rst='0' then cnt1<=0;
	elsif rising_edge(clk) then 
		 if cnt1>=1000 then cnt1<=0;count<='0';
		 elsif cnt1<=con then count<='1';cnt1<=cnt1+con;
		 else count<='0';cnt1<=cnt1+con;
		 end if;
		 end if;
end process;

end Behavioral;

--/*ANJIANQD.VHD*/--按键去抖模块
(同下,略去)

--/STEP_TOP.VHD*/--步进电机控制模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity step_top is
    Port (clk,add,sub,sel,rst,startstop:in std_logic;--时钟/加键/减键/换向键/复位/起止键
	 	step:out std_logic_vector(3 downto 0);  --步进电机四相输出
		shift:out std_logic_vector(3 downto 0);  --数码管位选
		data_led:out std_logic_vector(7 downto 0) );--七段数码管
end step_top;

architecture Behavioral of step_top is

component anjianqd is
    Port (clk,key:in std_logic;
    	keyo:out std_logic );
end component anjianqd;

component bianpin is
    Port (clk,sub,add,rst:in std_logic;
    	 count:out std_logic );
end component bianpin;

component step_motor is
    Port ( clk,rst : in std_logic;
	     sel : in std_logic;
	     clkkk:out std_logic;
	     control:out std_logic_vector(3 downto 0));
end component step_motor;

component ztsd is
    Port (clk,key,rst:in std_logic;
    	y:out std_logic ;
		sel:out std_logic);
end component ztsd;

component cepin is
    Port (clk,clk1,rst:std_logic;	
    	shift:out std_logic_vector(3 downto 0);
		data_led:out std_logic_vector(7 downto 0) );
end component cepin;

signal sel1,ss,sel2,count1,y1,y2,startstop1:std_logic;
signal step1,step2:std_logic_vector(3 downto 0);

begin
u1:anjianqd port map (clk=>clk,key=>sel,keyo=>sel1);
u2:bianpin port map (clk=>clk,sub=>sub,add=>add,count=>count1,rst=>rst);
u3:step_motor port map (clk=>count1,sel=>sel2,clkkk=>y2,control=>step1,rst=>rst);
u4:ztsd port map (clk=>clk,key=>sel1,y=>y1,sel=>sel2,rst=>rst);
u5:cepin port map (clk=>clk,clk1=>y2,shift=>shift,data_led=>data_led,rst=>rst);
u6:anjianqd port map (clk=>clk,key=>startstop,keyo=>startstop1);
step2(3)<=step1(3) and y1;
step2(2)<=step1(2) and y1;
step2(1)<=step1(1) and y1;
step2(0)<=step1(0) and y1;
step(3)<=step2(3) and ss;
step(2)<=step2(2) and ss;
step(1)<=step2(1) and ss;
step(0)<=step2(0) and ss;

process(rst,startstop1)  --启动/停止模块
variable cnt:std_logic;
begin
	if rst='0' then  cnt:='0';
	elsif rising_edge(startstop1) then 
	cnt:=not cnt;
	end if;
	case cnt is
	when '0'=>ss<='0';
	when '1'=>ss<='1';
	when others=>null;
	end case;
end process;
 
end Behavioral;

----------------------------------------------------------------------------------------------------------------------
-----------------------------------------伺服电机部分-----------------------------------------------------------
--/*ZTSDPWM.VHD*/--换向模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;