代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/493461/6393811
vhd cal_s1.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:20:49 04/02/08
-- Design Name:
-- Module Name: cal_s1 -
www.eeworm.com/read/492925/6414070
vhd pulse.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pulse IS
PORT(clk:IN STD_LOGIC;
d:IN STD_LOGIC_VECTOR(13 DOWNTO 0);
fout:OUT STD_LOGIC);
END p
www.eeworm.com/read/491336/6438731
bak frequency.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity frequency is
port(clk : in std_logic;
ain : in std_logic_vector(8 downto 0);
q : out
www.eeworm.com/read/491336/6438791
vhd frequency.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity frequency is
port(clk : in std_logic;
ain : in std_logic_vector(8 downto 0);
q : out
www.eeworm.com/read/491205/6441716
vhd mul3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mul3 is
port(in1,in2,in3:std_logic_vector(7 downto 0);
sela,selb,selc:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
e
www.eeworm.com/read/491205/6441739
vhd txmit.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmit is
port(
tx:out std_logic;
--data:in std_logic_vector(7 downto 0);
mclk_16,write:in std_logic
www.eeworm.com/read/491205/6441740
vhd rxcver.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity RXCVER is
--generic:constant:std_logic;
port
www.eeworm.com/read/490611/6449658
vhd regfile.vhd
--****************************************************************************************************
-- Register file for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 23.01.2003
--******
www.eeworm.com/read/490611/6449672
vhd alu.vhd
--****************************************************************************************************
-- ALU for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 16.12.2002
--****************
www.eeworm.com/read/490611/6449675
vhd controllogic.vhd
--****************************************************************************************************
-- Control logic for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 11.02.20