frequency.vhd

该程序是基于FPGA的硬件描述语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity frequency is
    port(clk : in std_logic;
         ain : in std_logic_vector(8 downto 0);
         q   : out  std_logic     );
end    frequency;


architecture one of frequency is
 signal f :std_logic;

 begin
    flag1:process(clk)
         variable Q: std_logic_vector(8 downto 0);
           begin 
            if clk'event and clk='1' then
                  if Q=511    then
                    f<='1';
                    Q:=ain;
                  else
                    f<='0';
                    Q:=Q+1; 
                  end if;
           end if;   
     end process flag1; 
              
    flag2:process(f)
          variable t: std_logic;
          begin

          if f'event and f='1'  then
             t:= not t;
              if t='1'  then  q<='1';
              else 
               q<='0';     
              end if;
          end if;
     end process flag2;
end one;