pulse.vhd

基于FPGA的乐曲发生器设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pulse IS
PORT(clk:IN STD_LOGIC;
       d:IN STD_LOGIC_VECTOR(13 DOWNTO 0);
       fout:OUT STD_LOGIC);
END pulse;
ARCHITECTURE behav OF pulse IS
SIGNAL count:STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL cq,cq1,cq2,load:STD_LOGIC;
BEGIN
   PROCESS(clk,load,d)
        BEGIN
           IF clk'EVENT AND clk='1' THEN
                IF load='1' THEN count<=d;
                ELSE count<=count-1;
                END IF;
           END IF;
  END PROCESS;
   PROCESS(count)
       BEGIN
           IF count=0 THEN cq<='1';
           ELSE cq<='0';END IF;
           load<=cq;
  END PROCESS;
  PROCESS(clk) 
      BEGIN
          IF clk'EVENT AND clk='1'THEN
          cq1<=cq;
          END IF;
  END PROCESS;
  PROCESS(cq1)
      BEGIN
           IF cq1'EVENT AND cq1='1'THEN
            cq2<=NOT cq2;
      END IF;
      fout<=cq2;
  END PROCESS;
END behav;