代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/382666/6286503

txt 带莫尔_米勒输出的状态机.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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txt 莫尔型状态机2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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txt 莫尔型状态机1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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vhd s_p2m_onechnl.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.dt16_pkg.all; entity sp2m_onechnl is port ( reset : in std_logic; fck32m :
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vhd count60.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count60 is port(inclk:in std_logic; outa:out std_logic_vector(6 downto 0); outb:out std_logic_v
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txt 米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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txt 带莫尔_米勒输出的状态机.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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www.eeworm.com/read/494695/6360569

txt 莫尔型状态机2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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txt 莫尔型状态机1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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www.eeworm.com/read/493793/6390967

vhd cnta.vhd

LIBRARY IEEE; -- 24进制计数器 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNTA IS PORT ( CLK : IN STD_LOGIC; U_D : IN STD_LO
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