count60.vhd

一个关于VHDL的cpld开发实验程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count60 is
  port(inclk:in std_logic;
       outa:out std_logic_vector(6 downto 0);
       outb:out std_logic_vector(6 downto 0));
end count60;
architecture count60_arch of count60 is
  signal ma,mb:std_logic_vector(3 downto 0);
  signal f:std_logic;
  signal md:std_logic_vector(24 downto 0);
begin
p1:process(inclk)
begin
  if inclk'event and inclk='1'then
    if md=24999999 then
       md<="0000000000000000000000000";
       f<=not f;
    else
       md<=md+1;
         f<=f;
    end if;
  end if;
end process p1;
p2:process(f)
begin 
  if f'event and f='1'then
    if ma=9 then
    ma<="0000";
      if mb=5 then
      mb<="0000";
      else
      mb<=mb+1;
      end if;
    else
    ma<=ma+1;
    end if;
  end if;
end process p2;
with ma select
outa<=   "0110000"when"0001",  --1
         "1101101"when"0010",  --2
         "1111001"when"0011",  --3
         "0110011"when"0100",  --4
         "1011011"when"0101",  --5
         "1011111"when"0110",  --6
         "1110000"when"0111",  --7
         "1111111"when"1000",  --8
         "1111011"when"1001",  --9
         "1110111"when"1010",  --A
         "0011111"when"1011",  --B
         "1001110"when"1100",  --C
         "0111101"when"1101",  --D
         "1001111"when"1110",  --E
         "1000111"when"1111",  --F
         "1111110"when others; --0
with mb select
outb<=   "0110000"when"0001",  --1
         "1101101"when"0010",  --2
         "1111001"when"0011",  --3
         "0110011"when"0100",  --4
         "1011011"when"0101",  --5
         "1011111"when"0110",  --6
         "1110000"when"0111",  --7
         "1111111"when"1000",  --8
         "1111011"when"1001",  --9
         "1110111"when"1010",  --A
         "0011111"when"1011",  --B
         "1001110"when"1100",  --C
         "0111101"when"1101",  --D
         "1001111"when"1110",  --E
         "1000111"when"1111",  --F
         "1111110"when others; --0
end count60_arch;