s_p2m_onechnl.vhd

此两文件是在MAXplusII环境下开发并运行通过的VHDL文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.dt16_pkg.all;

entity sp2m_onechnl is
  port (
        reset       : in    std_logic;
        fck32m      : in    std_logic; --来自背板的32M帧头
				clk32m      : in    std_logic; --来自背板的32M时钟				
        in2mhw_s    : in    std_logic;
        in2mhw_p    : out   std_logic_vector(7 downto 0)
        );
end sp2m_onechnl;

architecture arch_sp2m_onechnl of sp2m_onechnl is

  signal en_2m : std_logic;  
  signal en_2m_locked : std_logic_vector(3 downto 0);  
  signal count : std_logic_vector(3 downto 0);
  signal count1 : std_logic_vector(2 downto 0);
  signal in2mhw_p_tmp : std_logic_vector(7 downto 0);

begin

  process(reset,clk32m) --      fck32m
  begin
    if reset='1' then --='1' or 
      count<=(others => '0');
    elsif clk32m'event and clk32m='1' then
      count<=count+'1';
    end if;
  end process;
  
  process(clk32m)
  begin
    if clk32m'event and clk32m='1' then
      if count(3 downto 0) = "1111" then
        en_2m<='1';
      else
        en_2m<='0';
      end if;
    end if;
  end process;
  
  process(clk32m)
  begin
    if clk32m'event and clk32m='1' then
      en_2m_locked<=en_2m_locked(2 downto 0)&en_2m;
    end if;
  end process;
  
  
  process(fck32m,clk32m)
  begin
    if fck32m='1' then
       count1<=(others => '0');
    elsif clk32m'event and clk32m='1' then
      if en_2m='1' then
        count1<=count1+'1';
      end if;
    end if;
  end process;
 
  process(clk32m)
  begin
    if clk32m'event and clk32m='1' then
      if en_2m='1' then
        in2mhw_p_tmp<=in2mhw_p_tmp(6 downto 0) & in2mhw_s;
      end if;
    end if;
  end process;
  
  process(clk32m)
  begin
    if clk32m'event and clk32m='1' then
      if en_2m_locked(3)='1' and count1(2 downto 0)="100" then --011
        in2mhw_p<=in2mhw_p_tmp;
      end if;
    end if;
  end process;
      
  

end arch_sp2m_onechnl;