代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/305636/13764087
vhd uart.vhd
--
-- uart.vhd
--
-- 8-N-1 serial interface
--
-- wr, rd should be one cycle long => trde, rdrf goes 0 one cycle later
--
-- Author: Martin Schoeberl martin@good-ear.com
--
--
-- resources
www.eeworm.com/read/305636/13764088
vhd uart_tal.vhd
--
-- uart_tal.vhd
--
-- 8-N-1 serial interface
-- conf_reg: baud_rate and 2400, HW hs on/off, DTR
-- default: 111 => baud_rate, HW hs, DTR on
--
-- Author: Martin Schoeberl martin@good-ear.co
www.eeworm.com/read/305636/13764089
vhd uart_simple_broken.vhd
--
-- uart_simple.vhd
--
-- 8-N-1 serial interface
--
-- wr, rd should be one cycle long => trde, rdrf goes 0 one cycle later
--
-- Author: Martin Schoeberl martin@good-ear.com
--
--
-- res
www.eeworm.com/read/305631/13764310
vhd memioeth.vhd
--
-- memeth.vhd // new mem, io interface!!!
--
-- from mem to memeth in the old way!!!
--
-- TODO TODO split mem and io for different versions!!!!!!!!!
--
-- external memory and IO for JOP3 (
www.eeworm.com/read/304136/13799800
vhd vga_register_bank.vhd
-- ================================================================================
-- (c) 2005 Altera Corporation. All rights reserved.
-- Altera products are protected under numerous U.S. and fore
www.eeworm.com/read/303712/13810038
vhd vga_register_bank.vhd
-- ================================================================================
-- (c) 2005 Altera Corporation. All rights reserved.
-- Altera products are protected under numerous U.S. and fore
www.eeworm.com/read/303555/13812729
vhd sramcontroller.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------
entity sramcontroller is
port
(clock:in std_logic;
datain:in std_logic_vecto
www.eeworm.com/read/302931/13824676
vhd cnt6.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt6 is
port (clk, clr, ena: in std_logic;
cq: out std_logic_vector(3 downto 0);
www.eeworm.com/read/302931/13824681
vhd cnt10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port (clk, clr, ena: in std_logic;
cq: out std_logic_vector(3 downto 0);
www.eeworm.com/read/302931/13824707
vhd sec.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sec is
port (clk,ena: in std_logic;
cout: out std_logic;
ds, qs: out std_logic_vector(3 downto