sec.vhd

来自「VHDL的数字钟」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sec is
port (clk,ena: in std_logic;
         cout: out std_logic;
       ds, qs: out std_logic_vector(3 downto 0));
end sec;
architecture one of sec is
    signal dsi, qsi: std_logic_vector (3 downto 0);
begin
  process (clk, dsi, qsi, ena)
  begin
  if ena='1' then
   dsi <="0000";
   qsi <="0000";
   elsif clk'event and clk='1' then 
    if qsi="0101" and dsi="1000" then dsi<="1001";      
    elsif dsi<"1001" then dsi<=dsi+1;
      else dsi<="0000";
       if qsi<"0101" then qsi<=qsi+1;
       else qsi<="0000";
       end if;
    end if;
    if (qsi="0101" and dsi="1001") then cout <= '1';
    else cout<= '0';
    end if;
   end if;
 ds <= dsi;
 qs <= qsi;
  end process;
end one;