📄 sramcontroller.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------
entity sramcontroller is
port
(clock:in std_logic;
datain:in std_logic_vector(7 downto 0); --------data that is prepare to write in SRAM
memdatain:in std_logic_vector(7 downto 0); --------data reading from SRAM
memdataout:out std_logic_vector(7 downto 0); --------data writing in SRAM
dataout:out std_logic_vector(7 downto 0);
--------output data to appointed pin from SRAM
--------in order to validate the exactitude of the program
address:buffer integer range 0 to 2047; --------0->2^10 11-Bit address line
ce:out std_logic; --------connect to CE#
oe:out std_logic; --------connect to OE#
we:out std_logic --------connect to WE#
);
end;
---------------------------------------------
architecture controller of sramcontroller is
signal counter:integer range 0 to 9;
signal read:std_logic;
begin
process(clock)
begin
if rising_edge(clock)then
if counter=9 then
counter<=0;
else
counter<=counter+1;
end if;
end if;
end process;
-------------------------------------------------
process(clock)
begin
if rising_edge(clock)then
if counter=0 then
ce<='1';
if read='0'then
memdataout<=datain;
end if;
elsif counter=1 then
ce<='0';
elsif counter=2 then
if read='1'then
dataout<=memdatain;
end if;
elsif counter=3 then
ce<='1';
elsif counter=4 then
if address=2047 then ----------change to read mode if write as many as 2KB
address<=0;
read<='1';
else
address<=address+1; ----------continue writing data to the next ROM cell
end if; ----------if it has not reach 2KB
end if;
end if;
end process;
oe<=not read; ----------read='0'(in writing mode if OE# voltage
----------is high,it shows that SRAM can't output data)
---------------------------------------------------------------------------------------------------
we<=read; ----------read='0',(in writing mode,WE# voltage must be
----------is low,or it show be in reading mode)
end;
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