代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/323150/13348640
vhd cpremoveimag.vhd
-- ================================================================================
-- File: CPRemove.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.26.2006
-- Description:
-- This CP
www.eeworm.com/read/323150/13348664
vhd cpremovereal.vhd
-- ================================================================================
-- File: CPRemove.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.26.2006
-- Description:
-- This CP
www.eeworm.com/read/323150/13348690
vhd cpremove.vhd
-- ================================================================================
-- File: CPRemove.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.26.2006
-- Description:
-- This CP
www.eeworm.com/read/323150/13348751
vhd zeroremove.vhd
-- ================================================================================
-- File: ZeroRemove.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.29.2006
-- Description:
-- Zero R
www.eeworm.com/read/323150/13348882
vhd outputbuffer.vhd
-- ================================================================================
-- File: OutputBuffer.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.30.2006
-- Description:
-- Outp
www.eeworm.com/read/136890/13354784
vhd shift16.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
use altera.maxplus2.all;
LIBRARY lpm;
use lpm.lpm_components.ALL;
entity shift16 is
port
(
pi:in std_logic_vector (15 downto 0
www.eeworm.com/read/136613/13369531
vhd pulse.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pulse is
port (z,f:in std_logic_vector(5 downto 0);
clk:in std_logic;
q:out std_logic);
www.eeworm.com/read/322268/13383838
vhd input.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity input is
port(
clk: in std_logic;
reset: in std_l
www.eeworm.com/read/322148/13388381
vhd cdu99.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cdu99 is
port (
clk,reset:in std_logic;
count1 :out std_logic_v
www.eeworm.com/read/322148/13388411
vhd taxi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity taxi is
port (
clk,reset:in std_logic;--每来一个脉冲（代表运行了0.1公里)
en1:out