shift16.vhd

多路移位寄存器dsasg asgagvgdafgadtgertgdafgdafgda

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
use altera.maxplus2.all;
LIBRARY lpm;
use lpm.lpm_components.ALL;

entity shift16 is
port
(
	
	pi:in std_logic_vector (15 downto 0);
	po:out std_logic_vector(15  downto 0);
	clk:in std_logic;
	ldr:IN STD_LOGIC;
	si:in std_logic;
	so:out std_logic;
	rst:in std_logic	
);
end shift16;
ARCHITECTURE a OF shift16 IS	
	signal tempso:std_logic;
	signal tmp:std_logic_vector(15 downto 0);
BEGIN
	process(clk)
	begin
		if rst='1' then
			tmp<="0000000000000000";
		else      
			if clk'event and clk='1' then
				if ldr='1' then
					tmp<=pi;
				else
--					tempso<=tmp(15);
					tmp(15 downto 0)<=tmp(14 downto 0)&si;
				end if;
			end if;
		end if;
	end process;
	po<=tmp;
	so<=tmp(15);
END a;