pulse.vhd

来自「用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-」· VHDL 代码 · 共 55 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pulse is 
   port (z,f:in std_logic_vector(5 downto 0);
         clk:in std_logic;
         q:out std_logic);
end pulse;
architecture rtl of pulse is  
 begin 
    process(clk,z,f)
    variable zz:std_logic_vector(5 downto 0);
    variable a,b :std_logic;
    begin
        if clk'event and clk='1' then
            if b='0' then 
                if a='0' then
                    zz:=z-1;
                    a:='1';
                    q<='1';
                    if zz=0 then
                       b:='1';
                       a:='0';
                     end if;
                else zz:=zz-1;
                    if zz=0 then
                      b:='1';
                      a:='0'; 
                     end if;
                end if;
             
           else 
                if a='0' then
                   zz:=f-1;
                   a:='1';
                   q<='0';
                    if zz=0 then
                      b:='0';
                      a:='0'; 
                     end if;
                  else
                      zz:=zz-1;
                     if zz=0 then
                      b:='0';
                      a:='0'; 
                     end if;
                  end if;
               end if;
             end if;
       end process;
     end rtl;