代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
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www.eeworm.com/read/199789/7822624
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/199789/7822642
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/199789/7822672
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/434564/7859390
vhd testbench.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:50:28 04/27/2005
-- Design Name: loopback
-- Module Name: testbe
www.eeworm.com/read/299224/7879553
vhd tb.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity tb is
end tb;
architecture tb_arch of tb is
component MII_Proc is
port
(
www.eeworm.com/read/299194/7880395
vhd cnt3.vhd
--********************************************************************************--
-- --
-- 3-bit Bi-direction count
www.eeworm.com/read/399123/7887480
vhd poc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity poc is
port (clk: in std_logic;
reset:in std_logic;
rw: in std_logic;
d: in std_
www.eeworm.com/read/399123/7887657
vhd poc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity poc is
port (clk: in std_logic;
reset:in std_logic;
rw: in std_logic;
d: in std_
www.eeworm.com/read/399123/7887727
vhd poc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity poc is
port (clk: in std_logic;
reset:in std_logic;
rw: in std_logic;
d: in std_
www.eeworm.com/read/399120/7887835
vhd poc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity poc is
port (clk: in std_logic;
reset:in std_logic;
rw: in std_logic;
d: in std_