📄 cnt3.vhd
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--********************************************************************************--
-- --
-- 3-bit Bi-direction counter --
-- --
--********************************************************************************--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cnt3 is
port
(
clk :in std_logic;
dir :in std_logic;
reset :in std_logic;
q :out std_logic_vector (2 downto 0)
);
begin
end cnt3;
architecture behavior of cnt3 is
signal result: std_logic_vector(2 downto 0);
begin
process(reset, clk)
begin
if (reset='0') then
result<="000";
elsif (clk'event) and (clk='1') then
case dir is
when '1' =>
if (result/=7) then result<=result+1;
end if;
when '0' =>
if (result/=0) then result<=result-1;
end if;
when others =>
end case;
end if;
end process;
end behavior;
architecture structure of cnt3 is
signal add,sub,d,result:std_logic_vector (2 downto 0);
signal top,bottom:std_logic;
begin
q<=result;
top<=result(0) and result(1) and result(2);
bottom<=result(0) or result(1) or result(2);
add(0)<=(not result(0)) or top;
sub(0)<=(not result(0)) and bottom;
add(1)<=(result(0) xor result(1)) or top;
sub(1)<=not(result(0) xor result(1)) and bottom;
add(2)<=((result(0) and result(1)) xor result(2)) or top;
sub(2)<=not((result(0) or result(1)) xor result(2)) and bottom;
d(0)<=(sub(0) and (not dir)) or (add(0) and dir);
d(1)<=(sub(1) and (not dir)) or (add(1) and dir);
d(2)<=(sub(2) and (not dir)) or (add(2) and dir);
process(reset, clk)
begin
if (reset='0') then
result<="000";
elsif (clk'event)and(clk='1') then
result<=d;
end if;
end process;
end structure;
configuration conf of cnt3 is
for behavior
end for;
end conf;
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