poc.vhd

基于VHDL的POC编写与实现 实现三次握手

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity poc is
  port (clk:  in std_logic;
        reset:in std_logic;
        rw:   in std_logic;
        d:    in std_logic_vector(7 downto 0);
        cs:   in std_logic;
        rdy:  in std_logic;
        a:    in std_logic_vector(2 downto 0);
        pd:   buffer std_logic_vector(7 downto 0);
        tr:   out std_logic;
        psr:   buffer std_logic_vector(7 downto 0);
        nirq:  out std_logic);
end poc;
architecture behave of poc is
     signal br: std_logic_vector(7 downto 0);
     signal sr: std_logic_vector(7 downto 0);
     type state_type is(q0,q1,q2);
     signal state: state_type;
        begin
          process(clk,cs,rdy,reset)
             begin
                if cs='1' and reset='1' then
                     state<=q0;
                  elsif clk'event and clk='0' then
                      case state is
                           when q0=>
                              if a="000" then
                                    sr<=d;                             
                                  elsif sr(7)='1' and a="001" then
                                    br<=d;
                                    sr(7)<='0';
                                    elsif sr(7)='0' then
                                      state<=q1;
                                      tr<='1';
                              end if;
                           when q1=> 
                               if rw='1' and rdy='0' then
                                   pd<=br;
                                   state<=q2;
                                   tr<='0';
                               elsif rdy='1' then
                                       state<=q1;
                               end if;
                           when q2=> 
                               if rdy='1' then
                                      state<=q0;
                                      sr(7)<='1';
                                   else
                                       state<=q2;
                               end if;
                       end case;
                   end if;
            end process;
         psr<=sr;
         nirq<='0'  when sr(0)='1' and sr(7)='1'  else '1';
   end behave;