代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/441060/7676640
vhd ir.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;
entity ir is
port(memout:in std_logic_vector(15 downto 0);
clk:in st
www.eeworm.com/read/440064/7695045
vhd pci_cmdadr.vhd
--*****************************************************************************
-- FILE : PCI_CMDADR.vhd
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr : PCI Command Decoder
www.eeworm.com/read/439816/7701152
vhd cnta.vhd
LIBRARY IEEE; -- 24进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNTA IS
PORT ( CLK : IN STD_LOGIC;
U_D : IN STD_LO
www.eeworm.com/read/439191/7714989
vhd display.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(clock : in std_logic; --时钟采用20Hz
flash : in std_logic;
qin : in std_logic_vector(3
www.eeworm.com/read/438679/7728262
vhd interrupt.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
Entity interrupt is
Port(
LINT,READY,LCLK,RST : IN STD_LOGIC;
CCS,ADS,BLAST,WR : OUT STD_LOGIC;
www.eeworm.com/read/437422/7748581
txt ad_tlc5510.txt
--功能:用VHDL控制TLC5510从而实现对高速A/D器件TLC5510控制，进而处理
--TLC5510 VHDL控制程序
--文件名：TLC5510.vhd
--最后修改日期：2009.3.23 秦桂林
library ieee;
use ieee.std_logic_1164.all;
entity tlc5510 is
port(clk :in std_logi
www.eeworm.com/read/435744/7785954
vhd comcoun.vhd
--comcoun.vhd 7 segment com scan counter
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comcoun is
port(
clk : in std_logic;--synchronouse clock
f1k
www.eeworm.com/read/435558/7790424
vhd speaker.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity speaker is
port(clk:in std_logic;
tone:in std_logic_vector(10 downto 0);
spks:out std_logic);
end entity
www.eeworm.com/read/299989/7814993
vhd tb_sram_cf.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.all;
entity tb_SRAM_CF is
end tb_SRAM_CF;
ar
www.eeworm.com/read/199789/7822598
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in