display.vhd

实现交通灯控制器的vhdl编程

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(clock : in std_logic;    --时钟采用20Hz
     flash : in std_logic;
     qin : in std_logic_vector(3 downto 0);
     display : out std_logic_vector(6 downto 0));
end entity;
architecture behav of display is
signal timeout :integer range 0 to 21;
begin
  process(clock)
  begin
    if rising_edge(clock) then
      if (flash='0') then
        timeout<=0;
      else
        if (timeout=21) then
          timeout<=0;
        else
          timeout<=timeout+1;
      end if;
    end if;
    if (timeout<=11) then
      case qin is
        when "0000"=>display<="1000000";
        when "0001"=>display<="1111001";
        when "0010"=>display<="0100100";
        when "0011"=>display<="0110000";
        when "0100"=>display<="0011001";
        when "0101"=>display<="0010010";
        when "0110"=>display<="0000010";
        when "0111"=>display<="1111000";
        when "1000"=>display<="0000000";
        when "1001"=>display<="0011000";
        when others=>display<="1111111";
      end case;
    else
      display<="1111111";
    end if;
  end if;
  end process;
end behav;