tb_sram_cf.vhd

Use verilog and VHDL to implement the Motion Estimation function, work as the hardware accelerator.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.all; 


entity tb_SRAM_CF is
end tb_SRAM_CF;

architecture testbench of tb_SRAM_CF is
    -- Component declaration of the tested unit
    component SRAM_CF is
    port ( 
          CLK    :  in std_logic;
          CENA   :  in std_logic;
          AA     :  in std_logic_vector(15 downto 0);
          QA     :  out std_logic_vector(7 downto 0); 
          CENB   :  in std_logic;
          AB     :  in std_logic_vector(15 downto 0);
          DB     :  in std_logic_vector(7 downto 0)
          );
    end component;


component SRAM_PF is
    port ( 
          CLK    :  in std_logic;
          CENA_0 :  in std_logic;
          AA_0   :  in std_logic_vector(15 downto 0);
          QA_0   :  out std_logic_vector(7 downto 0); 
          CENA_1 :  in std_logic;
          AA_1   :  in std_logic_vector(15 downto 0);
          QA_1   :  out std_logic_vector(7 downto 0);
          CENB   :  in std_logic;
          AB     :  in std_logic_vector(15 downto 0);
          DB     :  in std_logic_vector(7 downto 0)
          );
 end component; 
 
 
 component motion_estimation is
 port (
       clk_sys      : in std_logic;
       rst_n        : in std_logic; 
       frm_start    : in std_logic;
       frm_cf_d     : in std_logic_vector(7 downto 0);
       frm_pf_da    : in std_logic_vector(7 downto 0);
       frm_pf_db    : in std_logic_vector(7 downto 0);
       frm_cf_addr  : out std_logic_vector(16 downto 0);
       frm_cf_rd    : out std_logic;
       frm_pf_addra : out std_logic_vector(16 downto 0);
       frm_pf_rda   : out std_logic;
       frm_pf_addrb : out std_logic_vector(16 downto 0);
       frm_pf_rdb   : out std_logic;
       vect_row     : out std_logic_vector(2 downto 0);
       vect_col     : out std_logic_vector(2 downto 0)      
--       vect_addr     : out std_logic_vector(16 downto 0)     
);
end component;
 
signal CENA_0 : std_logic;
signal AA_0 : std_logic_vector(15 downto 0);
signal QA_0 : std_logic_vector(7 downto 0); 
signal CENA_1 : std_logic;
signal AA_1 : std_logic_vector(15 downto 0);
signal QA_1 : std_logic_vector(7 downto 0);
signal CENB_p : std_logic;
signal AB_p : std_logic_vector(15 downto 0);
signal DB_p : std_logic_vector(7 downto 0);
 
 
    -- Stimulus signals - signals mapped to the input and inout ports of tested entity
constant delay : time := 2.5 ns;        
signal CLK : std_logic;
signal reset : std_logic;
signal CENA : std_logic;
signal AA : std_logic_vector(15 downto 0);
signal QA : std_logic_vector(7 downto 0);
signal CENB : std_logic;
signal AB : std_logic_vector(15 downto 0);
signal DB : std_logic_vector(7 downto 0);
signal frm_start : std_logic;
signal vect_row : std_logic_vector(2 downto 0);
signal vect_col : std_logic_vector(2 downto 0);
signal frm_cf_addr : std_logic_vector(16 downto 0);
signal frm_pf_addra : std_logic_vector(16 downto 0);
signal frm_pf_addrb : std_logic_vector(16 downto 0);


    -- Add your code here ...


begin
UUT_P : SRAM_PF 
    port map ( 
            CLK    => CLK,
            CENA_0 => CENA_0,
            AA_0   => AA_0,
            QA_0   => QA_0, 
            CENA_1 => CENA_1,
            AA_1   => AA_1,
            QA_1   => QA_1,
            CENB   => CENB_p,
            AB     => AB_p,
            DB     => DB_p
          );

    -- Unit Under Test port map
    UUT_C : SRAM_CF
        port map (
            CLK => CLK,
            CENA => CENA,
            AA => AA,
            QA => QA,
            CENB => CENB,
            AB => AB,
            DB => DB
        );
        

UUT_M  : motion_estimation
    port map(
       clk_sys      => CLK,
       rst_n        => reset,
       frm_start    => frm_start,
       frm_cf_d     => QA,
       frm_pf_da    => QA_0,
       frm_pf_db    => QA_1,
       frm_cf_addr  => frm_cf_addr,
       frm_cf_rd    => CENA,
       frm_pf_addra => frm_pf_addra,
       frm_pf_rda   => CENA_0,
       frm_pf_addrb => frm_pf_addrb,
       frm_pf_rdb   => CENA_1,
       vect_row     => vect_row,
       vect_col     => vect_col
--       vect_addr     => vect_addr  
);
    -- Add your stimulus here ...
    Reset_Gen: process
    begin       
 --       for i in 0 to 10000 loop
            reset <= '0'; wait for 50*delay; 
            reset <= not reset; wait for 1500 us;  
--        end loop;     
    end process;    
    CLK_Gen : process
    begin
        CLK <= '1'; wait for delay;
        CLK <= '0'; wait for delay;        
    end process CLK_Gen;  
    Start_Gen : process
    begin
        frm_start <= '0'; wait for 55*delay;
        frm_start <= '1'; wait for 500 us;        
    end process Start_Gen;   

    Constant_Gen : process
    begin
        CENB   <= '0';
        AB     <= "0000000000000000";
        DB     <= "00000000";
        CENB_P <= '0'; 
        AB_P   <= "0000000000000000";
        DB_P   <= "00000000";
        wait for 600 us;  
    end process Constant_Gen;  
    
    AA <= frm_cf_addr(15 downto 0);
    AA_0 <= frm_pf_addra(15 downto 0);
    AA_1 <= frm_pf_addrb(15 downto 0);

    
end testbench;

configuration CFG_OF_SRAM_CF of tb_SRAM_CF is
    for testbench
        for UUT_C : SRAM_CF
            use entity work.SRAM_CF(structural);
        end for;
    end for;
end CFG_OF_SRAM_CF;

configuration CFG_OF_SRAM_PF of tb_SRAM_CF is
    for testbench
        for UUT_P : SRAM_PF
            use entity work.SRAM_PF(structural);
        end for;
    end for;
end CFG_OF_SRAM_PF;