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Input 的代码
input.syn
JDF B
// Created by Version 2.1
PROJECT P2- P7- P8- Input PLD
DESIGN input Normal
DEVKIT M4A5-64/32-55VC48
ENTRY Schematic/VHDL
MODULE inputpld.vhd
MODSTYLE Input_PLD Normal
SYNTHESIS_TOOL Sy
input.grp
GROUP MACH_SEG_A p2_5_ p2_6_ p2_7_ p2_0_ p2_1_ p2_2_ p2_3_ p2_4_
GROUP MACH_SEG_B p7_0_ p7_1_ p7_2_ p7_3_ p8_6_ p8_7_
GROUP MACH_SEG_C un1_un19_wr N_50_iZ0
GROUP MACH_SEG_D data_4_ data_5_ dat
input.sdf
// SDF delay-file
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "input")
(DATE "5/28/2003 8:21:3")
(VENDOR "Lattice Semiconductor")
(PROGRAM "SDF Generator")
(VERSION "2.01.28.41.02 Data sh
input.trp
Timing Report for STAMP
// Project = input
// Family = mach4a
// Device = mach468a
// Speed = -5.5
// Voltage = 5.0
// Operating Condition = COM
// Data sheet version = RevD-8/2
input.mod
MODEL
MODEL_VERSION "1.0";
DESIGN "input";
DATE "Wed May 28 08:21:07 2003";
VENDOR "Lattice Semiconductor Corporation";
PROGRAM "STAMP Model Generator";
/* port name and type */
INPUT adresse
input.lco
[DEVICE]
Family = M4A5;
PartType = M4A5-64/32;
Package = 48TQFP;
PartNumber = M4A5-64/32-55VC48;
Speed = -5.5;
Operating_condition = COM;
EN_Segment = No;
Pin_MC_1to1 = No;
EN_PinReserve_IO =
input.tal
Design Name = input.tt4
~~~~~~~~~~~~~~~~~~~~~~~
*******************
* TIMING ANALYSIS *
*******************
Timing Analysis KEY:
One unit of delay time is equivalent to one pass
input.jid
. Input_PLD inputpld.vhd w:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd
input.svl
Part Number: M4A5-64/32-55VC48
Need not generate svf file according to the constraints, exit