📄 input.trp
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Timing Report for STAMP
// Project = input
// Family = mach4a
// Device = mach468a
// Speed = -5.5
// Voltage = 5.0
// Operating Condition = COM
// Data sheet version = RevD-8/2000
// Pass Bidirection = OFF
// Pass S/R = OFF
// Pass Latch = OFF
// T_SU Endpoints D/T inputs = ON
// T_SU Endpoints CE inputs = OFF
// T_SU Endpoints S/R inputs = OFF
// T_SU Endpoints RAM gated = ON
// Fmax of CE = ON
// Fmax of RAM = ON
// Location(From => To)
// Pin number: numeric number preceded by "p", BGA number as is
// Macrocell number: Segment#,GLB#,Macrocell#
// Segment#: starts from 0 (if applicable)
// GLB#: starts from A..Z, AA..ZZ
// Macrocell#: starts from 0 to 31
Section IO
//DESTINATION NODES;
p2[0] [bidi]
p2[1] [bidi]
p2[2] [bidi]
p2[3] [bidi]
p2[4] [bidi]
p2[5] [bidi]
p2[6] [bidi]
p2[7] [bidi]
p7[0] [bidi]
p7[1] [bidi]
p7[2] [bidi]
p7[3] [bidi]
p8[6] [bidi]
p8[7] [bidi]
data[0] [out]
data[1] [out]
data[2] [out]
data[3] [out]
data[4] [out]
data[5] [out]
data[6] [out]
data[7] [out]
data_0_.LH [reg]
data_1_.LH [reg]
data_2_.LH [reg]
data_3_.LH [reg]
data_4_.LH [reg]
data_5_.LH [reg]
data_6_.LH [reg]
data_7_.LH [reg]
un1_un19_wr.LH [reg]
data_0_.D [reg]
data_1_.D [reg]
data_2_.D [reg]
data_3_.D [reg]
data_4_.D [reg]
data_5_.D [reg]
data_6_.D [reg]
data_7_.D [reg]
un1_un19_wr.D [reg]
//SOURCE NODES;
adresse[0] [in]
adresse[1] [in]
adresse[2] [in]
adresse[3] [in]
adresse[4] [in]
adresse[5] [in]
cs [in]
rd [in]
reset [in]
wr [in]
data[0].Q [reg]
data[1].Q [reg]
data[2].Q [reg]
data[3].Q [reg]
data[4].Q [reg]
data[5].Q [reg]
data[6].Q [reg]
data[7].Q [reg]
un1_un19_wr.Q [reg]
Section tSU
tSU, tHD Level Location(From => To) Source Destination Reference_Clock
=========== ===== ==================== ====== =========== ===============
3.0, 3.0 1 p22 => D1 adresse[0] data_0_.D rd
3.0, 3.0 1 p22 => D5 adresse[0] data_1_.D rd
3.0, 3.0 1 p22 => D4 adresse[0] data_2_.D rd
3.0, 3.0 1 p22 => D8 adresse[0] data_3_.D rd
3.0, 3.0 1 p22 => D9 adresse[0] data_4_.D rd
3.0, 3.0 1 p22 => D13 adresse[0] data_5_.D rd
3.0, 3.0 1 p22 => D12 adresse[0] data_6_.D rd
3.0, 3.0 1 p22 => D0 adresse[0] data_7_.D rd
3.0, 3.0 1 p22 => C4 adresse[0] un1_un19_wr.D rd
3.0, 3.0 1 p23 => D1 adresse[1] data_0_.D rd
3.0, 3.0 1 p23 => D5 adresse[1] data_1_.D rd
3.0, 3.0 1 p23 => D4 adresse[1] data_2_.D rd
3.0, 3.0 1 p23 => D8 adresse[1] data_3_.D rd
3.0, 3.0 1 p23 => D9 adresse[1] data_4_.D rd
3.0, 3.0 1 p23 => D13 adresse[1] data_5_.D rd
3.0, 3.0 1 p23 => D12 adresse[1] data_6_.D rd
3.0, 3.0 1 p23 => D0 adresse[1] data_7_.D rd
3.0, 3.0 1 p23 => C4 adresse[1] un1_un19_wr.D rd
3.0, 3.0 1 p24 => D9 adresse[2] data_4_.D rd
3.0, 3.0 1 p24 => D13 adresse[2] data_5_.D rd
3.0, 3.0 1 p24 => C4 adresse[2] un1_un19_wr.D rd
3.0, 3.0 1 p25 => D9 adresse[3] data_4_.D rd
3.0, 3.0 1 p25 => D13 adresse[3] data_5_.D rd
3.0, 3.0 1 p25 => C4 adresse[3] un1_un19_wr.D rd
3.0, 3.0 1 p26 => D9 adresse[4] data_4_.D rd
3.0, 3.0 1 p26 => D13 adresse[4] data_5_.D rd
3.0, 3.0 1 p26 => C4 adresse[4] un1_un19_wr.D rd
3.0, 3.0 1 p27 => D9 adresse[5] data_4_.D rd
3.0, 3.0 1 p27 => D13 adresse[5] data_5_.D rd
3.0, 3.0 1 p27 => C4 adresse[5] un1_un19_wr.D rd
3.0, 3.0 1 p16 => D9 cs data_4_.D rd
3.0, 3.0 1 p16 => D13 cs data_5_.D rd
3.0, 3.0 1 p16 => C4 cs un1_un19_wr.D rd
3.0, 3.0 1 p44 => D1 p2[0] data_0_.D rd
3.0, 3.0 1 p45 => D5 p2[1] data_1_.D rd
3.0, 3.0 1 p46 => D4 p2[2] data_2_.D rd
3.0, 3.0 1 p47 => D8 p2[3] data_3_.D rd
3.0, 3.0 1 p48 => D9 p2[4] data_4_.D rd
3.0, 3.0 1 p1 => D13 p2[5] data_5_.D rd
3.0, 3.0 1 p2 => D12 p2[6] data_6_.D rd
3.0, 3.0 1 p3 => D0 p2[7] data_7_.D rd
3.0, 3.0 1 p9 => D1 p7[0] data_0_.D rd
3.0, 3.0 1 p10 => D5 p7[1] data_1_.D rd
3.0, 3.0 1 p11 => D4 p7[2] data_2_.D rd
3.0, 3.0 1 p12 => D8 p7[3] data_3_.D rd
3.0, 3.0 1 p13 => D12 p8[6] data_6_.D rd
3.0, 3.0 1 p14 => D0 p8[7] data_7_.D rd
Section tCO
tCO Level Location(From => To) Source Destination Register_Clock
=== ===== ==================== ====== =========== ==============
7.5 1 p20 => p33 rd data[0] data_0_.LH
7.5 1 p20 => p34 rd data[1] data_1_.LH
7.5 1 p20 => p35 rd data[2] data_2_.LH
7.5 1 p20 => p36 rd data[3] data_3_.LH
7.5 1 p20 => p37 rd data[4] data_4_.LH
7.5 1 p20 => p38 rd data[5] data_5_.LH
7.5 1 p20 => p39 rd data[6] data_6_.LH
7.5 1 p20 => p40 rd data[7] data_7_.LH
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