input.mod

TQ公司的STK16x开发系统的源码

MODEL
MODEL_VERSION "1.0";
DESIGN "input";
DATE "Wed May 28 08:21:07 2003";
VENDOR "Lattice Semiconductor Corporation";
PROGRAM "STAMP Model Generator";

/* port name and type */
INPUT adresse_0;
INPUT adresse_1;
INPUT adresse_2;
INPUT adresse_3;
INPUT adresse_4;
INPUT adresse_5;
INPUT cs;
INPUT rd;
INPUT reset;
INPUT wr;
OUTPUT data_0;
OUTPUT data_1;
OUTPUT data_2;
OUTPUT data_3;
OUTPUT data_4;
OUTPUT data_5;
OUTPUT data_6;
OUTPUT data_7;
INOUT p2_0;
INOUT p2_1;
INOUT p2_2;
INOUT p2_3;
INOUT p2_4;
INOUT p2_5;
INOUT p2_6;
INOUT p2_7;
INOUT p7_0;
INOUT p7_1;
INOUT p7_2;
INOUT p7_3;
INOUT p8_6;
INOUT p8_7;

/* timing arc definitions */
rd_data_0_delay: DELAY rd data_0;
rd_data_1_delay: DELAY rd data_1;
rd_data_2_delay: DELAY rd data_2;
rd_data_3_delay: DELAY rd data_3;
rd_data_4_delay: DELAY rd data_4;
rd_data_5_delay: DELAY rd data_5;
rd_data_6_delay: DELAY rd data_6;
rd_data_7_delay: DELAY rd data_7;

/* timing check arc definitions */
adresse_0_rd_setup: SETUP(POSEDGE) adresse_0 rd;
adresse_0_rd_hold: HOLD(POSEDGE) adresse_0 rd;
adresse_1_rd_setup: SETUP(POSEDGE) adresse_1 rd;
adresse_1_rd_hold: HOLD(POSEDGE) adresse_1 rd;
adresse_2_rd_setup: SETUP(POSEDGE) adresse_2 rd;
adresse_2_rd_hold: HOLD(POSEDGE) adresse_2 rd;
adresse_3_rd_setup: SETUP(POSEDGE) adresse_3 rd;
adresse_3_rd_hold: HOLD(POSEDGE) adresse_3 rd;
adresse_4_rd_setup: SETUP(POSEDGE) adresse_4 rd;
adresse_4_rd_hold: HOLD(POSEDGE) adresse_4 rd;
adresse_5_rd_setup: SETUP(POSEDGE) adresse_5 rd;
adresse_5_rd_hold: HOLD(POSEDGE) adresse_5 rd;
cs_rd_setup: SETUP(POSEDGE) cs rd;
cs_rd_hold: HOLD(POSEDGE) cs rd;
p2_0_rd_setup: SETUP(POSEDGE) p2_0 rd;
p2_0_rd_hold: HOLD(POSEDGE) p2_0 rd;
p2_1_rd_setup: SETUP(POSEDGE) p2_1 rd;
p2_1_rd_hold: HOLD(POSEDGE) p2_1 rd;
p2_2_rd_setup: SETUP(POSEDGE) p2_2 rd;
p2_2_rd_hold: HOLD(POSEDGE) p2_2 rd;
p2_3_rd_setup: SETUP(POSEDGE) p2_3 rd;
p2_3_rd_hold: HOLD(POSEDGE) p2_3 rd;
p2_4_rd_setup: SETUP(POSEDGE) p2_4 rd;
p2_4_rd_hold: HOLD(POSEDGE) p2_4 rd;
p2_5_rd_setup: SETUP(POSEDGE) p2_5 rd;
p2_5_rd_hold: HOLD(POSEDGE) p2_5 rd;
p2_6_rd_setup: SETUP(POSEDGE) p2_6 rd;
p2_6_rd_hold: HOLD(POSEDGE) p2_6 rd;
p2_7_rd_setup: SETUP(POSEDGE) p2_7 rd;
p2_7_rd_hold: HOLD(POSEDGE) p2_7 rd;
p7_0_rd_setup: SETUP(POSEDGE) p7_0 rd;
p7_0_rd_hold: HOLD(POSEDGE) p7_0 rd;
p7_1_rd_setup: SETUP(POSEDGE) p7_1 rd;
p7_1_rd_hold: HOLD(POSEDGE) p7_1 rd;
p7_2_rd_setup: SETUP(POSEDGE) p7_2 rd;
p7_2_rd_hold: HOLD(POSEDGE) p7_2 rd;
p7_3_rd_setup: SETUP(POSEDGE) p7_3 rd;
p7_3_rd_hold: HOLD(POSEDGE) p7_3 rd;
p8_6_rd_setup: SETUP(POSEDGE) p8_6 rd;
p8_6_rd_hold: HOLD(POSEDGE) p8_6 rd;
p8_7_rd_setup: SETUP(POSEDGE) p8_7 rd;
p8_7_rd_hold: HOLD(POSEDGE) p8_7 rd;

ENDMODEL