代码搜索：Gate
找到约 3,306 项符合「Gate」的源代码
代码结果 3,306
www.eeworm.com/read/38709/1116608
prjpcbstructure gate.prjpcbstructure
Record=TopLevelDocument|FileName=gate.SchDoc
www.eeworm.com/read/38709/1116617
schdoc gate.schdoc
www.eeworm.com/read/38709/1116618
sim gate.sim
Circuit: gate
Date: 星期六 二月 17 16:01:10 2007
Total elapsed time: 0.344 seconds.
www.eeworm.com/read/38709/1116620
sdf gate.sdf
www.eeworm.com/read/38709/1116621
nsx gate.nsx
gate
*SPICE Netlist generated by Advanced Sim server on 2007-2-17 16:01:09
*Add Node Bridge Data
ADVB1 [0 IN1 VCC][GND$AD IN1$AD VCC$AD] adc_mod
ADVB2 [IN1$DA VCC$DA][IN1 VCC] dac_mod
ADVB3 [OU
www.eeworm.com/read/480930/1305452
s gate.s
/*
* This file contains the code that gets mapped at the upper end of each task's text
* region. For now, it contains the signal trampoline code only.
*
* Copyright (C) 1999-2001 Hewlett-Packard
www.eeworm.com/read/480930/1306448
s gate.s
/* ------------------------------------------------------------------------------
*
* Linux/PARISC Project (http://www.thepuffingroup.com/parisc)
*
* System call entry code Copyright (c) Matthew W
www.eeworm.com/read/470676/1467773
vhd and_gate.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and_gate IS
PORT (a,b: IN std_logic;
x : OUT std_logic);
END and_gate;
ARCHITECTURE rtl OF and_gate IS
BEGIN
www.eeworm.com/read/470676/1467775
vhd and_gate.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and_gate IS
GENERIC (delay : time);
PORT (a : IN std_logic;
b : IN std_logic;
c : OUT std_log
www.eeworm.com/read/470676/1467778
vhd and_gate.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and_gate IS
PORT (a,b: IN std_logic;
x : OUT std_logic);
END and_gate;
ARCHITECTURE rtl OF and_gate IS
BEGIN