and_gate.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and_gate IS 
           GENERIC (delay  : time);
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
		 c  : OUT std_logic);
END and_gate;

ARCHITECTURE behave OF and_gate IS
BEGIN
	c <= a AND b AFTER (delay);
END behave;