代码搜索：Fall

找到约 1,303 项符合「Fall」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/154098/5642211

twr top_routed.twr

-------------------------------------------------------------------------------- Release 5.2i - Trace F.28 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. trce top_routed.ncd Design
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www.eeworm.com/read/154098/5642223

twr top_routed.twr

-------------------------------------------------------------------------------- Release 5.2i - Trace F.28 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. trce top_routed.ncd Design
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www.eeworm.com/read/258433/11864822

v mem_usr.v

/////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2005 Xilinx, Inc. // All Rights Reserved //////////////////////////////////////////////////////////////
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www.eeworm.com/read/187909/8592463

data d4_16.data

MODELDATA MODELDATA_VERSION "v1998.8" DESIGN "d4_16"; /* port drive, load, max capacitance and max transition in data file */ PORTDATA cs: MAXTRANS(0.0); reset: MAXTRANS(0.0); din: MAXTRAN
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www.eeworm.com/read/165920/10046144

data d_bcd.data

MODELDATA MODELDATA_VERSION "v1998.8" DESIGN "d_bcd"; /* port drive, load, max capacitance and max transition in data file */ PORTDATA cs_sw8: MAXTRANS(0.0); p_sw4: MAXTRANS(0.0); p_sw3: MAXT
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data top.data

MODELDATA MODELDATA_VERSION "v1998.8" DESIGN "top"; /* port drive, load, max capacitance and max transition in data file */ PORTDATA clk: MAXTRANS(0.0); enable: MAXTRANS(0.0); reset: MAXTRANS
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www.eeworm.com/read/397391/8053331

v fifo64.v

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// module FIFO2(clk, rst, datain, pin, wren, rden, dataout, pout, empty, full); input clk; inp
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v mem_phy_dq_iob.v

/////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2005 Xilinx, Inc. // All Rights Reserved //////////////////////////////////////////////////////////////
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www.eeworm.com/read/221024/14775774

html http:^^www.cs.wisc.edu^~shavlik^mlrg^old-scheds.html

Date: Tue, 05 Nov 1996 00:26:10 GMT Server: NCSA/1.5 Content-type: text/html Last-modified: Fri, 08 Mar 1996 21:17:47 GMT Content-length: 548 MLRG's Old Schedules of Papers to Di
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www.eeworm.com/read/116130/14987604

data pb.data

MODELDATA MODELDATA_VERSION "1.0"; DESIGN "pb"; DATE "Wed Feb 27 11:35:55 2002"; VENDOR "Lattice Semiconductor Co. Ltd."; PROGRAM "STAMP Model Generator"; /* port drive, max transition and max
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